An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at <formula formulatype="inline"> <tex Notation="TeX">${\rm VDD}=$</tex></formula> 0 V Achieving Zero Leakage With <formula formulatype="inline"><tex Notation="TeX">${<}$</tex> </formula>400-ns Wakeup Time for ULP Applications-Reference-Cited by-同舟云学术

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An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at ${\rm VDD}=$ 0 V Achieving Zero Leakage With ${<}$ 400-ns Wakeup Time for ULP Applications

Published:2014-01 Issue:1 Volume:49 Page:95-106
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Khanna Sudhanshu,Bartling Steven C.,Clinton Michael,Summerfelt Scott,Rodriguez John A.,McAdams Hugh P.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/6690141/06637100.pdf?arnumber=6637100

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3. FinFET 6T-SRAM All-Digital Compute-in-Memory for Artificial Intelligence Applications: An Overview and Analysis;Micromachines;2023-07-31

4. 1F-1T Array: Current Limiting Transistor Cascoded FeFET Memory Array for Variation Tolerant Vector-Matrix Multiplication Operation;IEEE Transactions on Nanotechnology;2023

5. A ReRAM-Based Non-Volatile and Radiation-Hardened Latch Design;Micromachines;2022-10-22

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