A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability-Reference-Cited by-同舟云学术

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A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability

Published:2011-02 Issue: Volume: Page:
ISSN:
Container-title:2011 IEEE International Solid-State Circuits Conference
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Author:

Sheu Shyh-Shyuan,Chang Meng-Fan,Lin Ku-Feng,Wu Che-Wei,Chen Yu-Sheng,Chiu Pi-Feng,Kuo Chia-Chen,Yang Yih-Shan,Chiang Pei-Chia,Lin Wen-Pin,Lin Che-He,Lee Heng-Yuan,Gu Pei-Yi,Wang Sum-Min,Chen Frederick T.,Su Keng-Li,Lien Chen-Hsin,Cheng Kuo-Hsing,Wu Hsin-Tun,Ku Tzu-Kun,Kao Ming-Jer,Tsai Ming-Jinn

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5740653/5746170/05746281.pdf?arnumber=5746281

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