Monolithic 3D Integrated BEOL Dual-Port Ferroelectric FET to Break the Tradeoff Between the Memory Window and the Ferroelectric Thickness
Author:
Affiliation:
1. Rochester Institute of Technology,USA
2. University of Stuttgart,Chair of Semiconductor Test and Reliability (STAR),Germany
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10117589/10117581/10118286.pdf?arnumber=10118286
Reference7 articles.
1. Temperature Dependence and Temperature-Aware Sensing in Ferroelectric FET
2. Analysis of Improved Performance Under Negative Bias Illumination Stress of Dual Gate Driving a- IGZO TFT by TCAD Simulation
3. On the Channel Percolation in Ferroelectric FET Towards Proper Analog States Engineering
4. Double-Gate W-Doped Amorphous Indium Oxide Transistors for Monolithic 3D Capacitorless Gain Cell eDRAM
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