Dual-port ferroelectric NAND flash memory for large memory window, QLC programmable and disturbance-free operations

Author:

Joh Hongrae1,Lee Sangho1,Ahn Jinho2,Jeon Sanghun1ORCID

Affiliation:

1. School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), 291, Daehak-ro, Yuseong-gu, Daejeon, 34141, Republic of Korea

2. Division of Materials Science and Engineering, Hanyang University, 222, Wangsimni-ro, Seonhdong-gu, Seoul, 04763, Republic of Korea

Abstract

Oxide channel dual-port FeNAND devices with low-temperature processing offer improved thermal stability, broader memory window, and enhanced reliability.

Funder

National Research Foundation of Korea

Ministry of Trade, Industry and Energy

Publisher

Royal Society of Chemistry (RSC)

Reference29 articles.

1. Charge-trapping device structure of SiO2∕SiN∕high-k dielectric Al2O3 for high-density flash memory

2. Performance Improvement in Charge-Trap Flash Memory Using Lanthanum-Based High- $\kappa$ Blocking Oxide

3. J.Jang , H.-S.Kim , W.Cho , H.Cho , J.Kim , S. I.Shim , J.-H.Jeong , B.-K.Son , D. W.Kim and J.-J.Shim , Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory. 2009 Symposium on VLSI Technology, 3_VNAND_endurance; IEEE , 2009, pp. 192–193

4. S.Whang , K.Lee , D.Shin , B.Kim , M.Kim , J.Bin , J.Han , S.Kim , B.Lee and Y.Jung , Novel 3-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell for 1Tb file storage application. 2010 international electron devices meeting , 4_VNAND; IEEE:, 2010, pp. 29.7.1–29.7.4

5. A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory

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