1. Charge-trapping device structure of SiO2∕SiN∕high-k dielectric Al2O3 for high-density flash memory
2. Performance Improvement in Charge-Trap Flash Memory Using Lanthanum-Based High- $\kappa$ Blocking Oxide
3. J.Jang , H.-S.Kim , W.Cho , H.Cho , J.Kim , S. I.Shim , J.-H.Jeong , B.-K.Son , D. W.Kim and J.-J.Shim , Vertical cell array using TCAT (Terabit Cell Array Transistor) technology for ultra high density NAND flash memory. 2009 Symposium on VLSI Technology, 3_VNAND_endurance; IEEE , 2009, pp. 192–193
4. S.Whang , K.Lee , D.Shin , B.Kim , M.Kim , J.Bin , J.Han , S.Kim , B.Lee and Y.Jung , Novel 3-dimensional dual control-gate with surrounding floating-gate (DC-SF) NAND flash cell for 1Tb file storage application. 2010 international electron devices meeting , 4_VNAND; IEEE:, 2010, pp. 29.7.1–29.7.4
5. A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory