Large Suppression to Lateral Charge Migration (LCM) Related Error Bits in Charge-Trap TLC 3D NAND Flash
Author:
Affiliation:
1. School of Information Science and Engineering, Shandong University,P. R. China
2. Shandong Sinochip Semiconductors Co., Ltd,P.R. China
Funder
National Natural Science Foundation of China
Natural Science Foundation of Shandong Province
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9962812/9962965/09962997.pdf?arnumber=9962997
Reference5 articles.
1. Program/Erase Cycling Enhanced Lateral Charge Diffusion in Triple-Level Cell Charge-Trapping 3D NAND Flash Memory
2. Lateral charge migration induced abnormal read disturb in 3D charge-trapping NAND flash memory
3. Retention Correlated Read Disturb Errors in 3-D Charge Trap NAND Flash Memory: Observations, Analysis, and Solutions
4. Automatic Data Repair Overwrite Pulse for 3D-TLC NAND Flash Memories with 38x Data-Retention Lifetime Extension
5. Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. One-shot Read Processing to Enhance Cold Data Retention in Charge-trap TLC 3D NAND Flash;2023 IEEE 15th International Conference on ASIC (ASICON);2023-10-24
2. FBEL: Enhanced LLR optimization algorithm based on the VSER prediction by flag bits in the bit-flipping scheme;IEICE Electronics Express;2023-06-10
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