FBEL: Enhanced LLR optimization algorithm based on the VSER prediction by flag bits in the bit-flipping scheme-Reference-Cited by-同舟云学术

FBEL: Enhanced LLR optimization algorithm based on the VSER prediction by flag bits in the bit-flipping scheme

Published:2023-06-10 Issue:11 Volume:20 Page:20230113-20230113
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Zhang Bo¹,Wang Qi¹,Yu Xiaolei¹,Li Qianhui²,He Jing¹,Wang Xianliang¹,Zhao Qianqi¹,Qiang Xuhong²,Huo Zongliang¹,Ye Tianchun¹

Affiliation:

1. Institute of Microelectronics of the Chinese Academy of Sciences

2. The University of Chinese Academy of Sciences

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/20/11/20_20.20230113/_pdf

Reference32 articles.

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