Program/Erase Cycling Enhanced Lateral Charge Diffusion in Triple-Level Cell Charge-Trapping 3D NAND Flash Memory
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8712125/8720395/08720412.pdf?arnumber=8720412
Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Impact of Program–Erase Operation Intervals at Different Temperatures on 3D Charge-Trapping Triple-Level-Cell NAND Flash Memory Reliability;Micromachines;2024-08-23
2. Reliability Improvement in Vertical NAND Flash Cells Using Adaptive Incremental Step Pulse Programming (A-ISPP) and Incremental Step Pulse Erasing (ISPE);IEEE Transactions on Electron Devices;2024-03
3. A Novel Protection Based on Current Correlation for DC Lines in Hybrid Cascaded Multi-Terminal HVDC Transmission System;IEEE Transactions on Power Delivery;2023-08
4. DNN-based error level prediction for reducing read latency in 3D NAND flash memory;Microelectronics Reliability;2023-08
5. Fabrication of a Hole‐Type Vertical Resistive‐Switching Random‐Access Array and Intercell Interference Induced by Lateral Charge Spreading;Advanced Electronic Materials;2022-12-23
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