Reliability Improvement in Vertical NAND Flash Cells Using Adaptive Incremental Step Pulse Programming (A-ISPP) and Incremental Step Pulse Erasing (ISPE)
Author:
Affiliation:
1. Department of Electrical and Computer Engineering and the Inter-University Semiconductor Research Center (ISRC), Seoul National University, Seoul, South Korea
2. Research and Development Division, SK hynix Inc., Icheon, South Korea
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Link
http://xplorestaging.ieee.org/ielx7/16/10457976/10399383.pdf?arnumber=10399383
Reference31 articles.
1. 256 Gb 3 b/Cell V-nand Flash Memory With 48 Stacked WL Layers
2. A world's first product of three-dimensional vertical NAND Flash memory and beyond
3. A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate
4. 13.4 A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface
5. NAND Flash Memory: Challenges and Opportunities
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