Runtime mechanisms for leakage current reduction in CMOS VLSI circuits-Reference-Cited by-同舟云学术

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Runtime mechanisms for leakage current reduction in CMOS VLSI circuits

Published:2002 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the International Symposium on Low Power Electronics and Design
language:
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Author:

Abdollahi A.,Fallah F.,Massoud

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/7994/22113/01029605.pdf?arnumber=1029605

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Pass Transistor-Based Pull-Up/Pull-Down Insertion Technique for Leakage Power Optimization in CMOS VLSI Circuits;Circuits, Systems, and Signal Processing;2016-02-16

2. Linear Statistical Leakage Analysis by Virtual Grid-Based Modeling;Statistical Performance Analysis and Modeling Techniques for Nanometer VLSI Designs;2012

3. Simultaneous Input Vector Control and Circuit Modification;Minimizing and Exploiting Leakage in VLSI Design;2009-10-20

4. Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities;Minimizing and Exploiting Leakage in VLSI Design;2009-10-20

5. An effective state-based predictive approach for leakage energy management on embedded systems;Design Automation for Embedded Systems;2009-08-08

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