Inverted SOA and Transient Non-Linearity of LDMOS Devices With RESURF-Implant
Author:
Affiliation:
1. Indian Institute of Technology,Centre for Applied Research in Electronics,Delhi,India
2. Indian Institute of Science,Department of Electronic Systems Engineering,Bengaluru,India
3. Semi-Conductor Laboratory,Mohali,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10117590/10117577/10118024.pdf?arnumber=10118024
Reference11 articles.
1. Short and long-term safe operating area considerations in LDMOS transistors
2. Best-in-class LDMOS with ultra-shallow trench isolation and p-buried layer from 18V to 40V in 0.18μm BCD technology
3. Optimizing the trade-off between the RDS(on) of power MOSFETs and linear mode perfomance by local modification of MOSFET gain
4. Theory Analyses of SJ-LDMOS With Multiple Floating Buried Layers Based on Bulk Electric Field Modulation
5. Automotive 130 nm smart-power-technology including embedded flash functionality
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