Hybrid Multisource Clock Tree Synthesis
Author:
Affiliation:
1. Intel
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9665417/9665446/09665516.pdf?arnumber=9665516
Reference18 articles.
1. Practical Full Chip Clock Distribution Design With a Flexible Topology and Hybrid Metaheuristic Technique
2. Robust chip-level clock tree synthesis for SOC designs
3. Clock Tree Synthesis Based On Rc Delay Balancing
4. Obstacle-Aware Clock-Tree Shaping During Placement
5. Cell-Based Semicustom Design of Zigzag Power Gating Circuits
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3. Harnessing Hybrid Clock Tree Topology to Boost PPA in Highly Utilized Designs;2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS);2023-11-19
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