DEVELOPMENT OF PARAMETERIZED MODEL OF LOGIC ELEMENTS AT CLOCK TREE SYNTHESIS

Abstract

Clock synthesis, routing optimization, placement and logic optimization are the three primary phases of physical design implementation. Since clock network synthesis uses at least 30% of the entire power budget, it is one of the crucial steps. Power consumption for high-performance blocks can reach 50% of the entire power. Not only would a high-quality clock tree will fix timing violations, but it will also minimize power usage and routing resource use. A new neural network based parameterized model is proposed in this paper, which can be used to obtain not only the list of logic elements, but it also can predict the circuits timing behaviour. Different ICs using SAED 14 and 32 nm technologies are designed using the proposed method.