1. DEVELOPMENT OF PARAMETERIZED MODEL OF LOGIC ELEMENTS AT CLOCK TREE SYNTHESIS;Proceedings;2024
2. Multisource Clock Tree Synthesis Through Sink Clustering and Fast Clock Latency Prediction;2023 IEEE International Symposium on Circuits and Systems (ISCAS);2023-05-21
3. Clock Optimization Techniques;2022 IEEE 5th International Conference on Electronics Technology (ICET);2022-05-13
4. Hybrid Multisource Clock Tree Synthesis;2021 28th IEEE International Conference on Electronics, Circuits, and Systems (ICECS);2021-11-28