A Study of Chip-Package Interaction with All-Copper Interconnections on Advanced Glass Substrates
Author:
Affiliation:
1. Georgia Institue of Technology,George W. Woodruff School of Mechanical Engineering,Atlanta,GA,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10564841/10564831/10564967.pdf?arnumber=10564967
Reference27 articles.
1. Wafer-Level Integration of an Advanced Logic-Memory System Through the Second-Generation CoWoS Technology
2. Large Size Multilayered Fan-Out RDL Packaging for Heterogeneous Integration
3. Embedded Multi-die Interconnect Bridge (EMIB) -- A High Density, High Bandwidth Packaging Interconnect
4. Advanced Under-Bump-Metal Scaling Solder Micro-Bump Interconnect Down to 10μm Pitch
5. Scaling Solder Micro-Bump Interconnect Down to $10\ \mu\mathrm{m}$ Pitch for Advanced 3D IC Packages
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