On Efficiency Enhancement of SHA-3 for FPGA-Based Multimodal Biometric Authentication
Author:
Affiliation:
1. Center for Nanoelectronics and VLSI Design and the School of Electronics Engineering, VIT Chennai, Chennai, Tamil Nadu, India
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/92/9739817/09715724.pdf?arnumber=9715724
Reference49 articles.
1. A hardware wrapper for the SHA-3 hash algorithms
2. Algebraic Fault Analysis of SHA-3 Under Relaxed Fault Models
3. Pipelined SHA-3 Implementations on FPGA
4. High Speed FPGA Implementation of Cryptographic KECCAK Hash Function Crypto-Processor
5. High throughput pipelined FPGA implementation of the new SHA-3 cryptographic hash algorithm
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