Efficient Hardware Implementation of Hash Algorithm SHA-3 for IoT Information Security
Author:
Affiliation:
1. School of Microelectronics, Hefei University of Technology,Hefei,China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10579949/10579951/10581578.pdf?arnumber=10581578
Reference13 articles.
1. NIST selects winner of secure hash algorithm (SHA-3) competition;Baum,2012
2. Comprehensive evaluation of high-speed and medium-speed implementations of five SHA-3 finalists using Xilinx and Altera FPGAs;Gaj;Cryptology ePrint Archive,2012
3. High throughput implementation of SHA3 hash algorithm on field programmable gate array (FPGA)
4. High-performance FPGA implementation of the secure hash algorithm 3 for single and multi-message processing
5. Enhancing the Hardware Pipelining Optimization Technique of the SHA-3 via FPGA
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