Pipelined SHA-3 Implementations on FPGA-Reference-Cited by-同舟云学术

Pipelined SHA-3 Implementations on FPGA

Published:2015-01-19 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the Second Workshop on Cryptography and Security in Computing Systems
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Author:

Michail Harris E.¹,Ioannou Lenos¹,Voyiatzis Artemios G.²

Affiliation:

1. Department of Electrical Engineering, Computer Engineering and Informatics, Cyprus University of Technology, Lemesos 3036, Cyprus

2. Industrial Systems Institute, "Athena" RIC in ICT and Knowledge Technologies, PSP building, Stadiou Str., Platani Patras, GR-26504, Greece

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/2694805.2694808

Reference23 articles.

1. High throughput pipelined FPGA implementation of the new SHA-3 cryptographic hash algorithm

2. FPGA Implementations of the Round Two SHA-3 Candidates

3. G. Bertoni J. Daemen M. Peeters G. van Assche and R. van Keer. Keccak implementation overview version 3.2 2012. http://keccak.noekeon.org/Keccak-implementation-3.2.pdf. G. Bertoni J. Daemen M. Peeters G. van Assche and R. van Keer. Keccak implementation overview version 3.2 2012. http://keccak.noekeon.org/Keccak-implementation-3.2.pdf.

4. High-speed implementation of the Keccak hash function on FPGA;Gholipour A.;International Journal of Advanced Computer Science,2012

5. X. Guo S. Huang L. Nazh and P. Schaumont. Fair and comprehensive performance evaluation of 14 second round SHA-3 ASIC implementations. NIST 2nd SHA-3 Candidate Conference 2010. http://csrc.nist.gov/groups/ST/hash/sha-3/Round2/Aug2010/. X. Guo S. Huang L. Nazh and P. Schaumont. Fair and comprehensive performance evaluation of 14 second round SHA-3 ASIC implementations. NIST 2nd SHA-3 Candidate Conference 2010. http://csrc.nist.gov/groups/ST/hash/sha-3/Round2/Aug2010/.

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