High throughput pipelined FPGA implementation of the new SHA-3 cryptographic hash algorithm-Reference-Cited by-同舟云学术

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High throughput pipelined FPGA implementation of the new SHA-3 cryptographic hash algorithm

Published:2014-05 Issue: Volume: Page:
ISSN:
Container-title:2014 6th International Symposium on Communications, Control and Signal Processing (ISCCSP)
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Author:

Athanasiou George S.,Makkas George-Paris,Theodoridis Georgios

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/6862736/6877795/06877931.pdf?arnumber=6877931

Cited by 21 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Comparative Study of Keccak SHA-3 Implementations;Cryptography;2023-11-20

2. A complete SHA-3 hardware library based on a high efficiency Keccak design;2023 IEEE Nordic Circuits and Systems Conference (NorCAS);2023-10-31

3. The Efficiency of High-performance SHA-3 Accelerator on the System Level;2023 International Symposium on Electrical and Electronics Engineering (ISEE);2023-10-19

4. Enhancing the Hardware Pipelining Optimization Technique of the SHA-3 via FPGA;Computation;2023-08-03

5. Hardware architecture for CRYSTALS-Kyber post-quantum cryptographic SHA-3 primitives;2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2023-06-18

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