FPGA Implementations of the Round Two SHA-3 Candidates-Reference-Cited by-同舟云学术

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FPGA Implementations of the Round Two SHA-3 Candidates

Published:2010-08 Issue: Volume: Page:
ISSN:
Container-title:2010 International Conference on Field Programmable Logic and Applications
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Author:

Baldwin Brian,Byrne Andrew,Lu Liang,Hamilton Mark,Hanley Neil,O'Neill Maire,Marnane William P.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5690273/5694025/05694284.pdf?arnumber=5694284

Cited by 36 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Lightweight Champions of the World: Side-Channel Resistant Open Hardware for Finalists in the NIST Lightweight Cryptography Standardization Process;ACM Transactions on Embedded Computing Systems;2024-07-17

2. Hardware acceleration design of the SHA-3 for high throughput and low area on FPGA;Journal of Cryptographic Engineering;2023-08-30

3. Enhancing the Hardware Pipelining Optimization Technique of the SHA-3 via FPGA;Computation;2023-08-03

4. Design and Implementation Secure Hash Algorithm 3 (SHA-3) using FPGA;2023 Third International Conference on Advances in Electrical, Computing, Communication and Sustainable Technologies (ICAECT);2023-01-05

5. Design of FPGA Circuit for SHA-3 Encryption Algorithm;Advances in Natural Computation, Fuzzy Systems and Knowledge Discovery;2023

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