Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes-Reference-Cited by-同舟云学术

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Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes

Published:2017-11 Issue:11 Volume:25 Page:3033-3044
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Lin Jin-Fa^ORCID,Sheu Ming-Hwa,Hwang Yin-Tsung,Wong Chen-Syuan,Tsai Ming-Yan

Funder

Ministry of Science and Technology, Taiwan

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/8079089/07997755.pdf?arnumber=7997755

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