Design of low delay low power hybrid logic based flip-flop using FinFET-Reference-Cited by-同舟云学术

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Design of low delay low power hybrid logic based flip-flop using FinFET

Published:2024-09 Issue: Volume:9 Page:100648
ISSN:2772-6711
Container-title:e-Prime - Advances in Electrical Engineering, Electronics and Energy
language:en
Short-container-title:e-Prime - Advances in Electrical Engineering, Electronics and Energy

Author:

Vali Syed Sadiq,N Ashok kumar

Publisher

Elsevier BV

Reference22 articles.

1. An ultra-low-voltage single-phase adaptive pulse latch with redundant toggling elimination;Huang,2020

2. A fully static true-single-phase-clocked dual-edge-triggered flip-flop for near-threshold voltage operation in IoT applications;Lee;IEEE Access,2020

3. An ultra-low-power fully-static contention-free flip-flop with complete redundant clock transition and transistor elimination;Shin;IEEE J. Solid-State Circuit.,2021

4. A redundancy eliminated flip-flop in 28 nm for low-voltage low-power applications;Shin;IEEE Solid-State Circuit. Lett,2020

5. A 0.4-V, 0.138-fJ/cycle single-phase-clocking redundant-transition-free 24T flip-flop with change-sensing scheme in 40-nm CMOS;Le;IEEE J. Solid-State Circuit.,2018

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