An Ultra-Low-Power Fully-Static Contention-Free Flip-Flop With Complete Redundant Clock Transition and Transistor Elimination-Reference-Cited by-同舟云学术

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An Ultra-Low-Power Fully-Static Contention-Free Flip-Flop With Complete Redundant Clock Transition and Transistor Elimination

Published:2021-10 Issue:10 Volume:56 Page:3039-3048
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Shin Gicheol^ORCID,Lee Eunyoung,Lee Jongmin,Lee Yongmin^ORCID,Lee Yoonmyung^ORCID

Funder

Basic Science Research and Basic Research Laboratory Program through the National Research Foundation of Korea

Ministry of Science and ICT

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9546917/09432755.pdf?arnumber=9432755

Cited by 15 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A power-efficient, single-phase, contention-free flip-flop with only three clock transistors;Microelectronics Journal;2024-10

2. Design of low delay low power hybrid logic based flip-flop using FinFET;e-Prime - Advances in Electrical Engineering, Electronics and Energy;2024-09

3. A Low-Power Single-Phase Split-Controlled Flip-Flop With No Redundant Switching;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

4. A Redundant-Transition-Free and Contention-Free Change-Sensing Flip-Flop;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-05

5. A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip;IEEE Journal of Solid-State Circuits;2024-02

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