A Redundancy Eliminated Flip-Flop in 28 nm for Low-Voltage Low-Power Applications
Author:
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8011414/8952828/09201534.pdf?arnumber=9201534
Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Design of low delay low power hybrid logic based flip-flop using FinFET;e-Prime - Advances in Electrical Engineering, Electronics and Energy;2024-09
2. Design of a Dual Change-Sensing 24T Flip-Flop in 65 nm CMOS Technology for Ultra Low-Power System Chips;Electronics;2022-03-10
3. 22nm CMOS pW Standby Power Flip-Flops with/without Security using Dynamic Leakage Suppression Logic;2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS);2022-03-01
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