22nm CMOS pW Standby Power Flip-Flops with/without Security using Dynamic Leakage Suppression Logic
Author:
Affiliation:
1. Nagoya University,Department of Electronics,Nagoya,Japan
Funder
JST
PRESTO
MIC
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9789038/9789039/09789041.pdf?arnumber=9789041
Reference9 articles.
1. Secure D flip-flop against side channel attacks
2. 8.2 Batteryless Sub-nW Cortex-M0+ processor with dynamic leakage-suppression logic
3. A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards;tiri;Proceedings of the 28th European Solid-State Circuits Conference,0
4. A Top-Down Approach to Building Battery-Less Self-Powered Systems for the Internet-of-Things
5. A Flip-Flop for the DPA Resistant Three-Phase Dual-Rail Pre-Charge Logic Family
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