Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies-Reference-Cited by-同舟云学术

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Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies

Published:2017-12 Issue:12 Volume:25 Page:3509-3520
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Scotti Giuseppe^ORCID,Bellizia Davide,Trifiletti Alessandro,Palumbo Gaetano

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/8118264/08048001.pdf?arnumber=8048001

Cited by 23 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A PRBS Generator Using Merged XOR-D Flip-Flop as Building Blocks;Circuits, Systems, and Signal Processing;2023-06-19

2. A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application;2023 18th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2023-06-18

3. An Improved Latch for SerDes Interface: Design and Analysis under PVT and AC Noise;Radioengineering;2023-06

4. Research and Design of Data Scrambling and Pseudo Random Sequence Sharing Circuit;2023 13th International Symposium on Advanced Topics in Electrical Engineering (ATEE);2023-03-23

5. A PVT tolerant latch in a 90-nm CMOS and performances under AC noise;International Journal of Electronics;2022-12-01

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