A PRBS Generator Using Merged XOR-D Flip-Flop as Building Blocks-Reference-Cited by-同舟云学术

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A PRBS Generator Using Merged XOR-D Flip-Flop as Building Blocks

Published:2023-06-19 Issue:11 Volume:42 Page:6813-6828
ISSN:0278-081X
Container-title:Circuits, Systems, and Signal Processing
language:en
Short-container-title:Circuits Syst Signal Process

Author:

Singh Mayank Kumar^ORCID,Singh Puneet,Chichhula Upendra,Mehra Hirensh,Das Devarshi Mrinal,Sakare Mahendra

Funder

SERB-DST Government of India

Publisher

Springer Science and Business Media LLC

Subject

Applied Mathematics,Signal Processing

Link

https://link.springer.com/content/pdf/10.1007/s00034-023-02425-z.pdf

Reference39 articles.

1. A. Amirany, K. Jafari, M.H. Moaiyeri, True random number generator for reliable hardware security modules based on a neuromorphic variation-tolerant spintronic structure. IEEE Trans. Nanotechnol. 19, 784–791 (2020). https://doi.org/10.1109/TNANO.2020.3034818

2. C.-H. Chang, J. Gu, M. Zhang, A review of 018$$\mu $$m full adder performances for tree structured arithmetic circuits. IEEE Trans. Very Large Scale /Integr. (VLSI) Syst. 13(6), 686–695 (2005). https://doi.org/10.1109/TVLSI.2005.848806

3. M. S. Chen, C. K. K. Yang, A low-power highly multiplexed parallel PRBS generator. In: Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, (2012), pp. 1–4, https://doi.org/10.1109/CICC.2012.6330664

4. R. Clarke, M.R. LeRoy, S. Raman, T.G. Neogi, R.P. Kraft, J.F. McDonald, 140 Gb/s Serializer using clock doublers in 90 nm SiGe technology. IEEE J. Solid State Circuits 50(11), 2703–2713 (2015). https://doi.org/10.1109/JSSC.2015.2472600

5. R. Dayalu, Low-voltage low-power CMOS full adder. IET Proc. Circuits Dev. Syst. 148(1), 19–24 (2001). https://doi.org/10.1049/ip-cds:20010170

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