A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits-Reference-Cited by-同舟云学术

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A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits

Published:2005-06 Issue:6 Volume:13 Page:686-695
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Chip-Hong Chang ,Jiangmin Gu ,Mingyan Zhang

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx5/92/31398/01458785.pdf?arnumber=1458785

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