A 270 fJ/op 5.8 GHz MOS Current Mode Logic D-Latch for High-Speed Application
Author:
Affiliation:
1. King Abdullah University of Science and Technology (KAUST),Computer, Electrical and Mathematical Science & Engineering Division,Thuwal,Saudi Arabia
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10161731/10161695/10161769.pdf?arnumber=10161769
Reference19 articles.
1. PDP and TPD Flexible MCML and MTCML Ultralow-Power and High-Speed Structures for Wireless and Wireline Applications
2. Feature - Power-aware design techniques for nanometer MOS current-mode logic gates: a design framework
3. A Multi-Folded MCML for Ultra-Low-Voltage High-Performance in Deeply Scaled CMOS
4. Design, Implementation and Performance Comparison of D- Latch Using Different Topologies
5. Impact of technology scaling on CMOS logic styles
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