A 1-6.5 Gbps Dual-Loop Cdr Design with Coarse-Fine Tuning Vco and Modified Dqfd

Author:

Wang Chua-Chin,Chodisetti L. S. S. Pavan Kumar,Liao Bo-Hao,Vellanki Pradyumna,Lee Tzung-Je

Publisher

Elsevier BV

Reference24 articles.

1. Low-power half-rate dual-loop clock-recovery system in 28-nm FDSOI;C Gimeno;Proc. 2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS),2018

2. A 0.42-3.45 Gb/s referenceless clock and data recovery circuit with counter-based unrestricted frequency acquisition;K.-S Son;IEEE Transactions on Circuits and Systems II: Express Briefs,2020

3. An improved wide-band referenceless CDR with UP pulse selector for frequency acquisition;P M Ha;Proc. 2020 International Conference on Advanced Technologies for Communications (ATC),2020

4. A clock and data recovery circuit with wide linear range frequency detector;K.-J Hsiao;Proc. 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT),2008

5. A wideband reference-less bidirectional continuous-rate frequency detector;P M Ha;Proc. 2019 3rd International Conference on Recent Advances in Signal Processing,2019

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