Combined HW/SW Drift and Variability Mitigation for PCM-Based Analog In-Memory Computing for Neural Network Applications-Reference-Cited by-同舟云学术

Combined HW/SW Drift and Variability Mitigation for PCM-Based Analog In-Memory Computing for Neural Network Applications

Published:2023-03 Issue:1 Volume:13 Page:395-407
ISSN:2156-3357
Container-title:IEEE Journal on Emerging and Selected Topics in Circuits and Systems
language:
Short-container-title:IEEE J. Emerg. Sel. Topics Circuits Syst.

Author:

Antolini Alessio¹^ORCID,Paolino Carmine²^ORCID,Zavalloni Francesco¹^ORCID,Lico Andrea¹,Scarselli Eleonora Franchi¹^ORCID,Mangia Mauro¹^ORCID,Pareschi Fabio²^ORCID,Setti Gianluca³^ORCID,Rovatti Riccardo¹^ORCID,Torres Mattia Luigi⁴,Carissimi Marcella⁴^ORCID,Pasotti Marco⁴^ORCID

Affiliation:

1. “‘Ercole De Castro” Research Centre on Electronic Systems for Information and Communication Technologies and the Department of Electrical Electronic and Information Engineering Engineering “Guglielmo Marconi,”, University of Bologna, Bologna, Italy

2. Department of Electronics and Telecommunications, Politecnico of Torino, Turin, Italy

3. CEMSE, King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi Arabia

4. STMicroelectronics, Agrate Brianza, Italy

Funder

Electronics Components and Systems for European Leadership (ECSEL) Joint Undertaking

JU through the European Union’s Horizon 2020 Research and Innovation Programme and France, Belgium, Czech Republic, Germany, Italy, Sweden, Switzerland, and Turkey

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/5503868/10078357/10035378.pdf?arnumber=10035378

Reference47 articles.

1. PCM-Based Analog Compute-In-Memory: Impact of Device Non-Idealities on Inference Accuracy

2. Characterization and Programming Algorithm of Phase Change Memory Cells for Analog In-Memory Computing

3. HERMES-Core—A 1.59-TOPS/mm² PCM on 14-nm CMOS In-Memory Compute Core Using 300-ps/LSB Linearized CCO-Based ADCs

4. Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory

5. Fully On-Chip MAC at 14 nm Enabled by Accurate Row-Wise Programming of PCM-Based Weights and Parallel Vector-Transport in Duration-Format

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3. A Bit-Line Biasing Circuit for Analog In-Memory Computing Based on Phase Change Memory;2024 19th Conference on Ph.D Research in Microelectronics and Electronics (PRIME);2024-06-09

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5. 28 nm FD-SOI embedded phase change memory exhibiting near-zero drift at 12 K for cryogenic spiking neural networks (SNNs);2024-04-26