Role of interfacial layer thickness on high-κ dielectric-based MOS devices

Abstract

An attempt has been made to investigate the role of interfacial layer (IL) and its thickness on HfO 2-based high-κ metal-oxide-semiconductor (MOS) devices. The capacitance–voltage (C–V) and current–voltage (I–V) characteristics have been simulated using Sentaurus TCAD software for two different IL thicknesses and at different substrate temperatures and doping concentrations. The device performance is found to be improved for an IL thickness of 1 nm at higher temperature but deteriorates with further increase in IL thickness. The capacitance value decreases with the increase in IL thickness and a flatband voltage shift (V fb ) due to the presence of interfacial charges at IL of higher thickness is observed. The analysis of I–V curve further shows that the leakage current change is more prominent at lower temperature for different IL thickness. The temperature dependence C–V curves show that the presence of 1 nm IL makes the device more reliable at elevated temperature.