Simulation Analysis of High-k Dielectric Junction less FET for Reduction of Subthreshold Leakage Current-Reference-Cited by-同舟云学术

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Simulation Analysis of High-k Dielectric Junction less FET for Reduction of Subthreshold Leakage Current

Published:2023-03-17 Issue: Volume: Page:
ISSN:
Container-title:2023 International Conference on Device Intelligence, Computing and Communication Technologies, (DICCT)
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Author:

Chaudhary Anshu¹,Kumar Singh Ashish²,Kumar Yadav Manoj¹

Affiliation:

1. MIET,Department of Electronics and Communication Engineering,Meerut,UP,250005

2. Chitkara University,Department of Electronics and Communication Engineering,Rajpura,Punjab,140401

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10110034/10110036/10110191.pdf?arnumber=10110191

Reference27 articles.

1. Impact of metal silicide source electrode on polarity gate induced source in junction less TFET;madan;Appl Phys A,2019

2. High-k Dielectric Thickness and Halo Implant on Threshold Voltage Control;mah;Journal of Telecommunication Electronic and Computer Engineering (JTEC),2018

3. Role of interfacial layer thickness on high-κ dielectric-based MOS devices

4. A comparative analytical approach for gate leakage current optimization in silicon MOSFET: A step to more reliable electronic device

5. First Principle Study of Spin Tunneling Current Under Field Effect in Magnetic Tunnel Junction for Possible Application in STT-RAM

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