Low-Power Design of High-Speed A/D Converters
Author:
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Cited by 8 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Replica-Amp Gain Enhancement Technique for an Operational Amplifier with Low Mismatch Sensitivity and High Voltage Swing;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2016
2. A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2013
3. Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers;IEICE Transactions on Electronics;2013
4. Low Power Consumption Column-Parallel Two-Stage Cyclic Analog-to-Digital Converters for 33-Megapixel 120-fps CMOS Image Sensor;The Journal of The Institute of Image Information and Television Engineers;2013
5. A 10 b 25 MS/s 4.8 mW 0.13 µm CMOS ADC with switched-bias power-reduction techniques;International Journal of Circuit Theory and Applications;2009-11
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