A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS-Reference-Cited by-同舟云学术

A 36-mW 1.5-GS/s 7-Bit Time-Interleaved SAR ADC Using Source Follower Based Track-and-Hold Circuit in 65-nm CMOS

Published:2013 Issue:7 Volume:E96.A Page:1552-1561
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

FURUTA Masanori¹,AKITA Ippei²,MATSUNO Junya¹,ITAKURA Tetsuro¹

Affiliation:

1. Corporate Research and Development Center, Toshiba Corporation

2. Department of Electrical & Electronic Information Engineering, Toyohashi University of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E96.A/7/E96.A_1552/_pdf

Reference13 articles.

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2. [2] M.S.W. Chen and R.W. Brodersen, “A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13µm CMOS,” IEEE J. Solid-State Circuits, vol.41, no.12, pp.2669-2680, Dec. 2006.

3. [3] E. Alpman, H. Lakdawala, L.R. Carley, and K. Soumyanath, “A 1.1V 50mW 2.5GS/s 7b time-interleaved C-2C SAR ADC in 45nm LP digital CMOS,” ISSCC Dig. Tech. Papers, pp.76-77, 2009.

4. [4] S. Gupta, M.A. Inerfield, and J. Wang, “A 1-GS/s 11-bit ADC with 55-dB SNDR, 250mW power realized by a high bandwidth scalable time-interleaved architecture,” IEEE J. Solid-State Circuits, vol.41, no.12, pp.2650-2657, Dec. 2006.

5. [5] K. Doris, E. Janssen, C. Nani, A. Zanikopoulos, and G. Weide, “A 480mW 2.6GS/s 10b time-interleaved ADC with 48.5dB SNDR up to Nyquist in 65nm CMOS,” IEEE J. Solid-State Circuits, vol.46, no.12, pp.2821-2833, Dec. 2011.