Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers-Reference-Cited by-同舟云学术

Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers

Published:2013 Issue:6 Volume:E96.C Page:838-849
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

LEE Hyunui¹,MIYAHARA Masaya¹,MATSUZAWA Akira¹

Affiliation:

1. Department of Physical Electronics, Tokyo Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E96.C/6/E96.C_838/_pdf

Reference26 articles.

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2. [2] B.D. Sahoo and B. Razavi, “A 10-Bit 1-GHz 33-mW CMOS ADC,” Dig. Symp. VLSI Circuits, pp.30-31, June 2012.

3. [3] B. Hernes, J. Bjornsen, T.N. Andersen, A. Vinje, H. Korsvoll, F. Telsto, A. Briskemyr, C. Holdo, and O. Moldsvor, “A 92.5mW 205MS/s 10b pipeline IF ADC implemented in 1.2V/3.3V 0.13µm CMOS,” IEEE ISSCC Dig. Papers, pp.462-463, Feb. 2007.

4. [4] A. Varzaghani and C.-K.K. Yang, “A 600MS/s 5-bit pipelined ADC for serial-link applications,” Dig. Symp. VLSI Circuits, pp.276-279, June 2004.

5. [5] A.M.A. Ali, A. Morgan, C. Dillon, G. Patterson, S. Puckett, P. Bhoraskar, H. Dinc, M. Hensley, R. Stop, S. Bardsley, D. Lattimore, J. Bray, C. Speir, and R. Sneed, “A 16b 250MS/s IF-sampling pipelined A/D converter with background calibration,” IEEE ISSCC Dig. Papers, pp.292-293, Feb. 2010.

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