A Study of High Temperature DC and AC Gate Stressing on the Performance and Reliability of Power SiC MOSFETs

Abstract

Although high-temperature measurements show a dramatic reduction in the bias-temperature stress-induced threshold-voltage instability of present state-of-the-art devices, a more thorough test methodology shows that several different conclusions may actually be drawn. The particular conclusion depends on the specific post-BTS measurement technique employed. Immediate room-temperature measurements suggest that significant oxide-trap activation may still be occurring. A significant, yet rapid, post-BTS recovery is observed as well. These results underline the importance of making both high-temperature and room-temperature measurements, as a function of stress and recovery time, to better ensure that the full effect of the BTS is observed. Initial AC BTS results suggest a similar level of device degradation as occurs from a DC BTS.