A novel single event upset hardened CMOS SRAM cell-Reference-Cited by-同舟云学术

A novel single event upset hardened CMOS SRAM cell

Published:2012 Issue:3 Volume:9 Page:140-145
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Zhang Guohe¹,Shao Jun¹,Liang Feng¹,Bao Dongxuan¹

Affiliation:

1. School of Electronic and Information Engineering, Xi'an Jiaotong University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

http://www.jstage.jst.go.jp/article/elex/9/3/9_3_140/_pdf

Reference7 articles.

1. Collection of Charge on Junction Nodes from Ion Tracks

2. [2] L. Liu, Y. F. Zhao, and S. Yue, “3D Simulation of Charge Collection and MNU in Highly-Scaled SRAM Design,” Proc. 5th Conf. INC, IMS and IDC, 10.1109/NCM.2009.121, pp. 242-246, 2009.

3. An SEU-hardened CMOS data latch design

4. SEU hardened memory cells for a CCSDS Reed-Solomon encoder

5. [5] M. N. Liu and S. Whitaker, “Low power SEU immune CMOS memory circuit,” IEEE Trans. Nucl. Sci., vol. 39, no. 6, pp. 1679-1684, 1992.

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