A novel SEU tolerant memory cell for space applications
Author:
Affiliation:
1. Shanghai Institute of Micro-system and Information Technology, Chinese Academy of Sciences
2. University of Chinese Academy of Sciences
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/15/17/15_15.20180656/_pdf
Reference10 articles.
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2. [2] P. E. Dodd and L. W. Massengill: “Basic mechanisms and modeling of single-event upset in digital microelectronics,” IEEE Trans. Nucl. Sci. 50 (2003) 583 (DOI: 10.1109/TNS.2003.813129).
3. [3] S. M. Jahinuzzaman, et al.: “A soft error tolerant 10T SRAMbit-cellwith differential read capability,” IEEE Trans. Nucl. Sci. 56 (2009) 3768 (DOI: 10.1109/TNS.2009.2032090).
4. [4] I.-S. Jung, et al.: “A novel sort error hardened 10T SRAM cells for low voltage operation,” MWSCAS (2012) 714 (DOI: 10.1109/MWSCAS.2012.6292120).
5. [5] S. Lin, et al.: “Analysis and design of nanoscale CMOS storage elements for single-event hardening with multiple-node upset,” IEEE Trans. Device Mater. Rel. 12 (2012) 68 (DOI: 10.1109/TDMR.2011.2167233).
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