Verification of SEU resistance in 65 nm high-performance SRAM with dual DICE interleaving and EDAC mitigation strategies
Author:
Publisher
Springer Science and Business Media LLC
Subject
Nuclear Energy and Engineering,Nuclear and High Energy Physics
Link
https://link.springer.com/content/pdf/10.1007/s41365-021-00979-8.pdf
Reference48 articles.
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2. L.W. Massengill, B.L. Bhuva, W.T. Holman, et al., Technology scaling and soft error reliability, in Paper Presented at the 2012 IEEE International Reliability Physics Symposium (California, USA 15–19 Apr. 2012). https://doi.org/10.1109/IRPS.2012.6241810
3. D. Tang, C. He, Y. Li et al., Soft error reliability in advanced CMOS technologies-trends and challenges. Sci. China Technol. Sci. 57, 1846–1857 (2014). https://doi.org/10.1007/s11431-014-5565-6
4. F. Moradi, G. Panagopoulos, G. Karakonstantis et al., Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology. Microelectron. J. 45, 23–34 (2014). https://doi.org/10.1016/j.mejo.2013.09.009
5. L.R. Rockett, Simulated SEU hardened scaled CMOS SRAM cell design using gated resistors. IEEE Trans. Nucl. Sci. 39, 1532–1541 (1992). https://doi.org/10.1109/23.173239
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