Wrap-Gate CNT-MOSFET Based SRAM Bit-Cell with Asymmetrical Ground Gating and Built-In Read-Assist Schemes for Application in Limited-Energy Environments

Abstract

This paper proposes a novel design of ultra-low power radiation-hardened single-ended SRAM bit-cell using the gate-all-around CNT-MOSFET based-gate diffusion input method (GAA CNT-GDI) for application in radiation-prone terrestrial (low-orbit) environments, where resources of circuit’s power supply are limited. In the structure of bit-cell to improve read-/hold-stability and expand write-ability several schemes have been used such as asymmetric virtual ground gating, built-in read-assist and the multi-diameter/chirality for CNTs. Also, in order to investigate single/double upsets, injection circuit model using the structure of the T-connected pseudo resistors (TPRs) has been proposed. The results of extensive Monte-Carlo (MC) simulations to evaluate the proposed bit-cell indicate expand write/hold/read static noise margins about 12.5%, 3.8%, and 8.2%, other figure of merits (FoMs), such as performance, yield, variability (μ/σ) and critical charge about 6.4 %, 5.8 % and almost 1.19 times respectively compared to studied cell design in counterpart technologies. Moreover, the suggested bit-cell has more robustness against radiation-induced soft errors with high reliability of data storage in the presence of critical voltage conditions, and better results in terms of other comprehensive FoMs as compared to state-of-the-art bit-cells in the 16 nm technology. The proposed bit-cell in a real application is used to store data from two-layer quick-response (2LQR) code-based in safety-critical environments. The results show the better performance of bit-cell in terms of a comprehensive FoM, which provides more effective trade-off between the hardware efficiency and quality metrics to evaluate the appropriate accuracy in the pixel-by-pixel image as compared to other well-known counterpart designs. Finally, the simulation results have validated that the suggested memory architecture can be a suitable candidate for application in devices such as terrestrial satellites that require both high reliability and cost-effectiveness.