Order Statistics Based Low-Power Flash ADC with On-Chip Comparator Selection-Reference-Cited by-同舟云学术

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Order Statistics Based Low-Power Flash ADC with On-Chip Comparator Selection

Published:2022-11-01 Issue:11 Volume:E105.A Page:1450-1457
ISSN:0916-8508
Container-title:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
language:en
Short-container-title:IEICE Trans. Fundamentals

Author:

KITAMURA Takehiro¹,ISLAM Mahfuzul¹,HISAKADO Takashi¹,WADA Osami¹

Affiliation:

1. Department of Electrical Engineering Graduate School of Engineering, Kyoto University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing

Link

https://www.jstage.jst.go.jp/article/transfun/E105.A/11/E105.A_2021KEP0007/_pdf

Reference23 articles.

1. [1] M. Flynn, C. Donovan, and L. Sattler, “Digital calibration incorporating redundancy of flash ADCs,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol.50, no.5, pp.205-213, 2003. 10.1109/tcsii.2003.811435

2. [2] C. Donovan, M.P. Flynn, and S. Member, “A “digital” 6-bit ADC in 0.25-um CMOS,” IEEE J. Solid-State Circuits, vol.37, no.3, pp.432-437, 2002. 10.1109/4.987096

3. [3] G. Keskin, J. Proesel, J.O. Plouchart, and L. Pileggi, “Exploiting combinatorial redundancy for offset calibration in flash ADCs,” IEEE J. Solid-State Circuits, vol.46, no.8, pp.1904-1918, 2011. 10.1109/jssc.2011.2157255

4. [4] C.-Y. Chen, M.Q. Le, and K.Y. Kim, “A low power 6-bit flash ADC with reference voltage and common-mode calibration,” IEEE J. Solid-State Circuits, vol.44, no.4, pp.1041-1046, 2009. 10.1109/jssc.2009.2014701

5. [5] K.L.J. Wong and C.K.K. Yang, “Offset compensation in comparators with minimum input-referred supply noise,” IEEE J. Solid-State Circuits, vol.39, no.5, pp.837-840, 2004. 10.1109/jssc.2004.826317

Cited by 4 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Fully Integrated Digital LDO With Adaptive Sampling and Statistical Comparator Selection;IEEE Solid-State Circuits Letters;2024

2. Design of Reference-free Flash ADC With On-chip Rank-based Comparator Selection Using Multiple Comparator Groups;IPSJ Transactions on System and LSI Design Methodology;2024

3. An Adaptive-Sampling Digital LDO with Statistical Comparator Selection Achieving 99.99% Maximum Current Efficiency and 0.25ps FoM in 65nm;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05

4. Demonstration of Order Statistics Based Flash ADC in a 65nm Process;Proceedings of the 28th Asia and South Pacific Design Automation Conference;2023-01-16

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