Design of Reference-free Flash ADC With On-chip Rank-based Comparator Selection Using Multiple Comparator Groups
Author:
Affiliation:
1. Department of Electrical Engineering, Graduate School of Engineering, Kyoto University
Publisher
Information Processing Society of Japan
Link
https://www.jstage.jst.go.jp/article/ipsjtsldm/17/0/17_36/_pdf
Reference17 articles.
1. [1] Weaver, S., Hershberg, B., Kurahashi, P., Knierim, D. and Moon, U.K.: Stochastic flash analog-to-digital conversion, IEEE Trans. Circuits Syst. I: Regul. Pap., Vol.57, No.11, pp.2825-2833 (2010).
2. [2] Fahmy, A., Liu, J., Kim, T. and Maghari, N.: An all-digital scalable and reconfigurable wide-input range stochastic ADC using only standard cells, IEEE Trans. Circuits Syst. II: Express Briefs, Vol.62, No.8, pp.731-735 (2015).
3. [3] Jeon, M.K., Yoo, W.J., Kim, C.G. and Yoo, C.: A stochastic flash analog-to-digital converter linearized by reference swapping, IEEE Access, Vol.5, pp.23046-23051 (2017).
4. [4] Uto, S. and Ohhata, K.: Stochastic subranging ADC using variable comparator offset technique, IEEE Int. Symp. Radio-Frequency Integr. Technol. RFIT 2020, No.September, pp.232-234 (2020).
5. [5] Van der Plas, G., Decoutere, S. and Donnay, S.: A 0.16pJ/conversion-step 2.5mW 1.25GS/s 4b ADC in a 90nm digital CMOS process, IEEE Int. Solid-State Circuits Conf., pp.566-567 (2006).
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