A Fully Integrated Digital LDO With Adaptive Sampling and Statistical Comparator Selection-Reference-Cited by-同舟云学术

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A Fully Integrated Digital LDO With Adaptive Sampling and Statistical Comparator Selection

Published:2024 Issue: Volume:7 Page:163-166
ISSN:2573-9603
Container-title:IEEE Solid-State Circuits Letters
language:
Short-container-title:IEEE Solid-State Circuits Lett.

Author:

Yamaguchi Shun¹^ORCID,Hisakado Takashi¹^ORCID,Wada Osami¹^ORCID,Islam Mahfuzul¹^ORCID

Affiliation:

1. Department of Electrical Engineering, Kyoto University, Kyoto, Japan

Funder

Japan Society for the Promotion of Science (JSPS) KAKENHI

Rohm Joint Research Program

activities of VDEC, The University of Tokyo, in collaboration with NIHON SYNOPSYS G.K., Cadence Design Systems, and Mentor Graphics

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Link

http://xplorestaging.ieee.org/ielx7/8011414/10359146/10491593.pdf?arnumber=10491593

Reference12 articles.

1. An Output-Capacitor-Free Synthesizable Digital LDO Using CMP-Triggered Oscillator and Droop Detector

2. Output-Capacitorless Tri-Loop Digital Low Dropout Regulator Achieving 99.91% Current Efficiency and 2.87 fs FOM

3. A Fully Integrated Digital LDO With Coarse–Fine-Tuning and Burst-Mode Operation

4. A Digital LDO in 22-nm CMOS With a 4-b Self-Triggered Binary Search Windowed Flash ADC Featuring Analog Layout Generator Framework

5. A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency

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