A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency-Reference-Cited by-同舟云学术

A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency

Published:2021-09-13 Issue: Volume: Page:
ISSN:
Container-title:ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)
language:
Short-container-title:

Author:

Bang Jooeun,Choi Seojin,Yoo Seyeon,Lee Jeonghyun,Kim Juyeop,Choi Jaehyouk

Funder

National Research Foundation of Korea

IC Design Education Center

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9567713/9567736/09567821.pdf?arnumber=9567821

Cited by 6 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Four-Phase Time-Based Switched-Capacitor LDO With 13-ns Settling Time at 0.5-V Input for Energy-Efficient Computing in SoC Applications;IEEE Journal of Solid-State Circuits;2024-02

2. A Fully Integrated Digital LDO With Adaptive Sampling and Statistical Comparator Selection;IEEE Solid-State Circuits Letters;2024

3. An Adaptive-Sampling Digital LDO with Statistical Comparator Selection Achieving 99.99% Maximum Current Efficiency and 0.25ps FoM in 65nm;2023 IEEE Asian Solid-State Circuits Conference (A-SSCC);2023-11-05

4. A Self-Clocked and Variation-Tolerant Unified Voltage-and-Frequency Regulator for In-Order Executed Digital Loads;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-11

5. A Capacitor-Less Digital LDO Regulator With Synthesizable PID Controller Achieving 99.75% Efficiency and 93.3-ps Response Time in 65 nm;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-05