A Capacitor-Less Digital LDO Regulator With Synthesizable PID Controller Achieving 99.75% Efficiency and 93.3-ps Response Time in 65 nm
Author:
Affiliation:
1. Department of Electrical and Computer Engineering, University of Michigan, Ann Arbor, MI, USA
Funder
Defense Advanced Research Projects Agency
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering
Link
http://xplorestaging.ieee.org/ielx7/8920/10124122/10071546.pdf?arnumber=10071546
Reference9 articles.
1. A Current Efficient 10mA Analog-Assisted Digital Low Dropout Regulator with Dynamic Clock Frequency in 65nm CMOS
2. Modeling and analysis of system stability in a distributed power delivery network with embedded digital linear regulators
3. A Universal Modular Hybrid LDO With Fast Load Transient Response and Programmable PSRR in 14-nm CMOS Featuring Dynamic Clamp Strength Tuning
4. A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency
5. Capacitorless Self-Clocked All-Digital Low-Dropout Regulator
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1. A Technology-Agnostic Method for Digital LDO Synthesis and Layout Automation;Proceedings of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design;2024-08-05
2. A Capacitor-less Hybrid LDO for Low Frequency Supply Noise Suppression Achieving 99.87% Efficiency and 3.32ps Response Time in 65nm;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19
3. Automated design flow for synthesizable ADPLL: From specification to GDS;AEU - International Journal of Electronics and Communications;2024-04
4. Wide operation range high-voltage linear regulator chip design;Electrical Engineering;2023-10-13
5. A Double-Edge-Triggered Digital LDO with Built-In Adaptive VCO Clock for Fast Transient Response and Low Power Consumption;Electronics;2023-09-29
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