Automated design flow for synthesizable ADPLL: From specification to GDS

Author:

Kwon KyuminORCID,Wentzloff David D.

Funder

Defense Advanced Research Projects Agency

Publisher

Elsevier BV

Reference17 articles.

1. Late breaking results: analog circuit generator based on deep neural network enhanced combinatorial optimization;Hakhamaneshi,2019

2. Rethinking sparsity in performance modeling for analog and mixed circuits using spike and slab models;Alawieh,2019

3. Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits;Perrott,2002

4. A capacitor-less digital LDO regulator with synthesizable PID controller achieving 99.75% efficiency and 93.3-ps response time in 65 nm;Cherivirala;IEEE Trans Circuits Syst II,2023

5. An open source compatible framework to fully autonomous digital LDO generation;Cherivirala,2023

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