An Adaptive-Sampling Digital LDO with Statistical Comparator Selection Achieving 99.99% Maximum Current Efficiency and 0.25ps FoM in 65nm
Author:
Affiliation:
1. Kyoto University,Kyoto,Japan
Funder
The University of Tokyo
Synopsys
Mentor Graphics
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10347557/10347908/10347918.pdf?arnumber=10347918
Reference10 articles.
1. An output-capacitor-free synthesizable digital LDO using CMP-triggered oscillator and droop detector;Oh;JSSC,2022
2. Output-Capacitorless Tri-Loop Digital Low Dropout Regulator Achieving 99.91% Current Efficiency and 2.87 fs FOM
3. A Fully Integrated Digital LDO With Coarse–Fine-Tuning and Burst-Mode Operation
4. A Digital LDO in 22nm CMOS with a 4b Self-triggered Binary Search Windowed Flash ADC Featuring Automatic Analog Layout Generator Framework
5. A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A Fully Integrated Digital LDO With Adaptive Sampling and Statistical Comparator Selection;IEEE Solid-State Circuits Letters;2024
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