Demonstration of Order Statistics Based Flash ADC in a 65nm Process

Author:

Islam Mahfuzul1,Kitamura Takehiro1,Hisakado Takashi1,Wada Osami1

Affiliation:

1. Kyoto University, Kyoto, Japan

Publisher

ACM

Reference6 articles.

1. Stochastic Flash Analog-to-Digital Conversion

2. A Stochastic Flash Analog-to-Digital Converter Linearized by Reference Swapping

3. Stochastic Subranging ADC Using Variable Comparator Offset Technique

4. J. Proesel , G. Keskin , J. O. Plouchart , and L. Pileggi , " An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection," in IEEE Cust . Integr. Circuits Conf. , vol. 4 , 2010 , pp. 8 -- 11 . J. Proesel, G. Keskin, J. O. Plouchart, and L. Pileggi, "An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection," in IEEE Cust. Integr. Circuits Conf., vol. 4, 2010, pp. 8--11.

5. T. Kitamura , M. Islam , T. Hisakado , and O. Wada , " Flash ADC utilizing offset voltage variation with order statistics based comparator selection," in IEEE Int . Symp. Qual. Electron. Des. (ISQED) , 2021 , pp. 103 -- 108 . T. Kitamura, M. Islam, T. Hisakado, and O. Wada, "Flash ADC utilizing offset voltage variation with order statistics based comparator selection," in IEEE Int. Symp. Qual. Electron. Des. (ISQED), 2021, pp. 103--108.

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