Investigation of Field Concentration Effects in Arch Gate Silicon–Oxide–Nitride–Oxide–Silicon Flash Memory
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering
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2. Exploiting Asymmetric Errors for LDPC Decoding Optimization on 3D NAND Flash Memory;IEEE Transactions on Computers;2020-04-01
3. A Progressive Performance Boosting Strategy for 3-D Charge-Trap NAND Flash;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-11
4. Boosting the Performance of 3D Charge Trap NAND Flash with Asymmetric Feature Process Size Characteristic;Proceedings of the 54th Annual Design Automation Conference 2017;2017-06-18
5. Impact of continuing scaling on the device performance of 3D cylindrical junction-less charge trapping memory;Journal of Semiconductors;2015-09
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