An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending
Author:
Publisher
Zhejiang University Press
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing
Link
https://link.springer.com/content/pdf/10.1631/FITEE.2100432.pdf
Reference29 articles.
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3. Asif S, Kong YN, 2015. Design of an algorithmic Wallace multiplier using high speed counters. Proc 10th Int Conf on Computer Engineering & Systems, p.133–138. https://doi.org/10.1109/icces.2015.7393033
4. Chang CH, Gu JM, Zhang MY, 2004. Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits. IEEE Trans Circ Syst I Regul Pap, 51(10):1985–1997. https://doi.org/10.1109/tcsi.2004.835683
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